Taiwan - OIP Ecosystem Forum Agenda

Sheraton Hsinchu Hotel – November 6 (Wednesday)

Time Plenary Session
08:30 – 09:30 Registration & Ecosystem Pavilion
09:30 – 09:45 Welcome Remarks
09:45 – 10:30 TSMC Keynote & Guest Speech
10:30 – 11:00 Coffee Break & Ecosystem Pavilion
TSMC Technical Talks
11:00 – 11:30 3Dblox 2024: Maximize 3DIC Design Productivity

TSMC

AI-powered EDA Solutions for Design PPA, QoR and Productivity Enhancement

TSMC

OIP Partner Technical Talks
HPC & 3DFabric Track Mobile, IoT & Automotive Track
11:30 – 11:50 Routing of Multi-Chiplet TSMC 3DFabric technologies

Cadence / AMD

New approach that targets EM/IR hotspot analysis and fixing with mPower and Calibre DesignEnhancer

Siemens EDA

11:50 – 12:10 Ansys-Synopsys-TSMC Solve the 3DIC Multiphysics Challenges

Synopsys / Ansys

Groundbreaking SRAM Repair Toolset: Pre-integrated Siemens Tessent MBIST with eMemory’s NeoFuse OTP

eMemory / Siemens EDA

12:10 – 12:30 Effective methods to reuse and automate bump creation for chiplets in 3DIC designs

Synopsys / AMD

Leveraging AI to accelerate debug with Calibre Design Solutions

Siemens EDA

12:30 – 13:30 Lunch & Ecosystem Pavilion
13:30 – 13:50 A Collaborative Study on 2.5D System in Package for Better Quality and Reliability of High Bandwidth Memory

SK hynix

Low-Power Communication IC Design Verified by AI-Powered Simulation Flow

Siemens EDA / THine Electronics

13:50 – 14:10 Simplifying requirements and flows of SoIC technology for Stacked die design with TSMC 3Dblox and Cadence Integrity 3D-IC Platform

Cadence / GUC

AI Driven Layout Optimization For T-Coil Matching Networks

Ansys / AMD

14:10 – 14:30 GDDR Memory for High-Performance AI Inference

Cadence / Rambus

Insights into the Synopsys-TSMC UCIe IP on N5 and CoWoS Test Chip

Synopsys

14:30 – 14:50 3DIC Physical Implementation and SoIC-X Silicon Testing Results

GUC

Innovative design methodology for custom layout automation helping drive AI/ML

Cadence

14:50 – 15:20 Coffee Break & Ecosystem Pavilion
15:20 – 15:40 Efficient 3D Chiplet Stacking Using TSMC SoIC Technology

Alchip / Synopsys

Die-to-Die Physical-Aware Interconnect Testing Using 3Dblox For Reduced Manufacturing Test Cost

Siemens DI SW / TSMC

15:40 – 16:00 A comprehensive IP validation methodology for Microsoft’s AI and high-performance compute chips

Siemens EDA / Microsoft

M31's Advanced MIPI Solutions on TSMC N5/N5A: Driving Efficiency and Performance in Automotive Applications

M31 Technology

16:00 – 16:20 Distributed and GPU-accelerated 3D EM Simulations for IC and 3DIC Silicon Photonics Applications with Peakview

Lorentz Solution / NVIDIA

New RISC-V Solutions for Infrastructure and Datacenters

SiFive

16:20 – 16:40 The Road Toward Unified-MultiPhysics-Design-Environment for High NA EUV Process Technology

National Taiwan University

From Specification to Layout: An AI-driven Automation Design Flow for Analog Circuits

National Taiwan University

16:40 – 16:55 Lucky Draw