|
Time
|
Plenary Session
|
| 08:30 – 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 – 09:45 |
Welcome Remarks |
| 09:45 – 10:15 |
TSMC Keynote |
| 10:15 – 10:45 |
Coffee Break & Ecosystem Pavilion |
|
TSMC Technical Talks |
| 10:45 – 11:15 |
3Dblox 2024: Maximize 3DIC Design Productivity
TSMC
|
AI-powered EDA Solutions for Design PPA, QoR and Productivity Enhancement
TSMC
|
|
OIP Partner Technical Talks |
|
HPC & 3DFabric Track |
Mobile, IoT & Automotive Track |
| 11:15 – 11:35 |
Routing of Multi-Chiplet TSMC 3DFabric technologies
Cadence
/ AMD
|
Early-Stage High Local Noise Coverage Dynamic-IR Analysis using RedHawk-SC SigmaDVD
UNISOC
/ Ansys
|
| 11:35 – 11:55 |
An Efficient Early-Prototyping Power-Thermal Analysis for 3DIC design
sanechips
/ ansys
|
A comprehensive IP validation methodology for Microsoft’s AI and high-performance compute chips
Siemens EDA
/ Microsoft
|
| 11:55 – 12:15 |
Effective methods to reuse and automate bump creation for chiplets in 3DIC designs
Synopsys
/ AMD
|
Application of Cadence Virtuoso Studio Schematic & Analog Layout Migration Flow in Migration Across Different TSMC Process Nodes
Cadence
/ Sanechips
|
| 12:15 – 13:30 |
Lunch & Ecosystem Pavilion |
| 13:30 – 13:50 |
The early EMIR analysis of Interposer-substrate-PCB in the AI system
Iluvatar
/ Ansys
|
AI Optimization In Serdes&D2D SI Simulation
Sanechips
/ Cadence DesignSystems, Inc
|
| 13:50 – 14:10 |
3DIC Physical Implementation and SoIC-X Silicon Testing Results
GUC
|
An exploration of the Multi-Corner Multi-Mode (MCMM) selection method for processor-core timing closure and power optimization
Sanechips Technology Co., Ltd
/ Synopsys，Inc.
|
| 14:10 – 14:30 |
Multi-die design for TSMC COUPE with unified electronic and photonic design solutions
Synopsys
/ Ansys
|
New approach that targets EM/IR hotspot analysis and fixing with mPower and Calibre DesignEnhancer
Siemens EDA
|
| 14:30 – 14:50 |
GDDR Memory for High-Performance AI Inference
Cadence
/ Rambus
|
A "Shift-Left" Layout Parasitics Analysis Flow For AMS Design In FinFET
SANECHIPS
/ Ansys
|
| 14:50 – 15:20 |
Coffee Break & Ecosystem Pavilion |
| 15:20 – 15:40 |
Efficient 3D Chiplet Stacking Using TSMC SoIC Technology
Alchip
/ Synopsys
|
A Fusion Solution of SYN and PNR Based on Cerebrus
Sanechips
/ Cadence
|
| 15:40 – 16:00 |
High Performance UCIe Chiplet supports Die-to-Die and Chip-to-Chip for Cost Effective HPC System
innosilicon
|
Accelerating the Verification of High-Frequency Mixed-Signal Components via Jivaro Pro Advanced Parasitic Reduction
Silvaco
/ Silicon Creations
|
| 16:00 – 16:20 |
Ansys-Synopsys-TSMC Solve the 3DIC Multiphysics Challenges
Synopsys
/ Ansys
|
The low voltage USB4 PHY for Type-C applications
M31 Technology
|
| 16:20 – 16:35 |
Lucky Draw |
